Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One such application is for memory devices or cells. A variety of memory device types have been developed including, for example, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM). A variety of PROM memory devices have been developed which allow for reprogramming. Among the most useful are flash memory cells and electrically erasable PROM (EEPROM) cells. The programming of these memory devices can be erased, for example, by sending an electrical signal through the cells.
One conventional memory device is shown in FIG. 1. The memory device 100 generally includes a semiconductor substrate 102 on which a polysilicon plate 104, commonly referred to as a floating gate, is disposed. The floating gate 104 is used to define the state (e.g., a binary "0" or "1") of the memory device 100. Source and drain regions 106 are typically formed in regions of the substrate 102 adjacent the floating gate 104 by heavily doping these regions with a dopant material of a desired conductivity. The conductivity of the doped region depends on the type of impurity used to dope the region.
A channel region 108 is formed in the semiconductor substrate 102 beneath the floating gate electrode 104 and between the source and drain regions 106. The channel 108 is often lightly doped with a dopant material having a conductivity type opposite to that of the source and drain regions 106. The floating gate electrode 104 is generally separated from the substrate 102 by an insulating layer 1 10, typically an oxide layer such as SiO.sub.2. The insulating layer 110 is provided to restrain current from flowing between the control gate electrode 104 and the source and drain regions 106 or channel region 108.
The memory device further includes a second polysilicon plate 112, commonly referred to as a control gate, disposed over the floating gate 104. The control gate 112 generally receives an input signal to control operation of the device. As noted above, the floating gate 104 is used to define the state of the memory device 100. Generally, the state of the device 100 is determined by the presence or absence of a conductive channel region 108, which in turn depends on the presence or absence of charge on the floating gate 104. Typically, the presence of charge on the floating gate 104 indicates a binary "1" state, while the absence of charge indicates a binary "0" state. The floating gate 104 is generally separated from the control gate 112 by a dielectric layer 116, typically an oxide or nitride layer such as silicon dioxide, silicon nitride, or oxynitride. The insulating layer 116 is provided to prevent charge from leaking from the floating gate electrode 112 and to control the speed of the device 100.
The dielectric layer 116 plays an important role in the operation of the memory device 100. For instance, the speed of the memory device 100 depends on the capacitive characteristics of the dielectric layer 116. In addition, the reliability of the memory device 100 depends on the ability of the floating gate 104 to retain charge over extended periods of time. The ability to retain charge also depends, at least in part, on the characteristics of the dielectric layer 116. Thus, in order to improve the performance of memory devices, new dielectric structures and fabrication techniques are needed.